Capacitive voltage divider for power management

ABSTRACT

A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage divider (CVD) coupled to the PMIC. The CVD is configured to receive the primary supply voltage of the memory sub-system as an input and provide a modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the MPSV is not higher than the uppermost PMIC supply voltage.

TECHNICAL FIELD

The present disclosure relates generally to memory sub-systems, and more particularly, to a capacitive voltage divider for power management for memory sub-systems.

BACKGROUND

A memory sub-system can be a storage system, such as a solid-state drive (SSD), and can include one or more memory components that store data. The memory components can, for example, include volatile memory components and non-volatile memory components. The memory sub-system can include a controller that can manage the memory components and allocate data to be stored at the memory components. In general, a host system may utilize a memory sub-system to store data at the memory components and to retrieve data from the memory components via the controller. Various memory sub-systems include a power management component to manage power allocation.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

FIG. 1 illustrates an example computing environment that includes a memory sub-system in accordance with some embodiments of the present disclosure.

FIG. 2 illustrates an example of a power management component in accordance with some embodiments of the present disclosure.

FIG. 3 is a flow diagram of an example method to operate a capacitive voltage divider in accordance with some embodiments of the present disclosure.

FIG. 4 is an additional flow diagram of the example method illustrated in FIG. 3 in accordance with some embodiments of the present disclosure.

FIG. 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to a capacitive voltage divider (CVD) for power management in a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a solid-state drive (SSD). Various memory sub-systems can include a power management (PM) component to manage receipt of a primary supply voltage from an electrical power source and to appropriately allocate electrical power (e.g., magnitudes of voltages) so as to be compatible with operation of one or more memory components of a particular memory sub-system. The PM component can include a power management integrated circuit (PMIC).

Some conventional PMIC components can include etched or hard-coded logic to provide control over the various requirements of a memory device. In approaches that utilize etched or hard-coded logic, the PMIC component can be configured to provide control over the various requirements of a particular memory device. As a result, such conventional PMIC components can only be used for a particular application and/or for a particular memory device. If the requirements of the memory device change, for example, such conventional PMIC components can cease to function or operate properly, which can result in stockpiles of conventional PMIC components becoming obsolete and therefore non-fungible.

In order to reduce wasted stockpiles of PMIC components that are etched or include hard-coded logic, some conventional PMIC components employ eFuses, which can allow for aspects of the PMIC component to be changed after manufacture. In PMIC components that employ eFuses, if a particular PMIC component is no longer used or needed, for example due to changes in various requirements of a memory device for which the PMIC component is designed, one or more of the eFuses may be burned (e.g., blown). This may allow for the PMIC component to be reprogrammed to a certain extent to function with a memory device that has had its various requirements changed after manufacture of the PMIC component. However, due to the nature of eFuses (e.g., when an eFuse has been blown it cannot be blown again), conventional PMIC components that utilize eFuses can only be reprogrammed a finite number of times.

Further, conventional PMIC components that use eFuses are often programmed (e.g., the eFuses are blown) after manufacture and/or prior to a point of sale to operate in accordance with a particular set of memory device requirements. If the memory device requirements change after the eFuses are blown, the conventional PMIC component can generally not be reprogrammed, which can result in the stockpiles of conventional PMIC components becoming obsolete and therefore non-fungible. Accordingly, similar to conventional approaches in which PMIC components are etched or hard-coded, conventional approaches to PMIC components that utilize eFuses can lead to wasted stockpiles of PMIC components. For example, because of the single use nature of eFuses, when the requirements of a memory device for which the PMIC component is designed change, PMIC components that utilize eFuses can become non-fungible.

A conventional PMIC can be configured to convert the primary supply voltage of a memory device to various output voltages (e.g., rails) for operation of the memory components. However, various conventional PMICs are configured to operate at a particular supply voltage, or within a limited range of supply voltages. Accordingly, different conventional PMICs, which are not designed to operate at other primary supply voltages, are designed to accommodate different primary supply voltages in order to, for example, avoid damage to constituent components of the PMIC. In conventional implementations, a PMIC can receive a primary supply voltage at, for example, 12 volts (V) and can reduce the primary supply voltage in a single operation using a voltage converter (e.g., a buck regulator, among other possible types of regulators on the PMIC). A voltage converter configured to perform a large voltage reduction (e.g., from 12V to 1V) uses more energy than a voltage converter configured to perform a smaller voltage reduction (e.g., from 4V to 1V). In addition, such a voltage converter can occupy more area and/or volume (e.g., on a circuit board) than a voltage converter configured to perform a smaller voltage reduction.

Moreover, a reduction of a magnitude of the primary supply voltage (e.g., below a threshold voltage) can result in loss of data from memory components (e.g., an array of memory cells) in conventional implementations. For example, interruption of a connection of a memory device to a primary power supply can result in loss of data from an array of volatile memory cells upon which data is stored and/or upon which various operations are being performed, among other possible consequences of reduction of the primary supply voltage.

Aspects of the present disclosure address the above, and other deficiencies, by providing the CVD, as described herein, as part of the PM component. Including the CVD between an input of the primary supply voltage and the PMIC configured to be compatible with operating at a lower voltage than the primary supply voltage can address the above, and other, deficiencies of a conventional PMIC implementation. For example, the CVD can convert a primary supply voltage of 12V or higher to a PMIC supply voltage in a range of 3-5V that is compatible with operation of the PMIC. The CVD can be configured to accommodate multiple different primary supply voltages by converting the multiple different primary supply voltages into a supply voltage (e.g., within a limited range of supply voltages) compatible with operation of a particular PMIC. The CVD of the PM component can be configured to store multiple configuration profiles, as described further herein, that can be dynamically selected based on various requirements resulting from changes to a magnitude of the primary supply voltages input from a primary power supply to the memory sub-system via the CVD.

A two-stage implementation of the CVD configured as such, along with using the PMIC to further adjust the PMIC supply voltage to voltages compatible with operation of memory components of the memory sub-system, can provide improved energy efficiencies. Such an improved energy efficiency can be above energy efficiencies achieved with conventional one-stage reductions using a single voltage converter (e.g., a buck regulator) or conventional two-stage reductions using two such voltage converters for such a large voltage reduction. Moreover, fewer voltage converters and/or a voltage converter configured to perform a smaller voltage reduction than a voltage converter configured to perform a larger voltage reduction (e.g., a voltage converter that performs a 4V to 1V rather than 12V to 1V reduction) can occupy less area and/or volume (e.g., within a PMIC on a circuit board). A CVD combined with a PMIC, which is configured to operate at a voltage output from the CVD, also can cost less than a conventional PMIC that is configured to operate at, for example, 12V and produce an output voltage of 1V.

FIG. 1 illustrates an example computing environment 100 that includes a memory sub-system 104 in accordance with some embodiments of the present disclosure. The computing environment 100 illustrated in FIG. 1 shows various components that are part of, or that are coupled to, the memory sub-system 104. For example, a primary power supply (PPS) 101 can be coupled to the memory sub-system 104. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

The memory sub-system 104 can include a PM component 110. The PM component 110 can, in various embodiments, include a CVD 114 and a PMIC 116. The memory sub-system 104 can include the PM component 110 coupled to a memory device controller 105 (hereinafter referred to as “controller”).

The PM component 110 on memory sub-system 104 can include a PMIC 116 configured to adjust a particular input voltage so as to be compatible with operation of various components of memory sub-system 104. The PMIC 116 can be compatible with operation at an uppermost PMIC supply voltage. The PMIC supply voltage is lower than a primary supply voltage 102 of the memory sub-system 104 provided by the PPS 101. The PMIC 116 can be configured to output one or more voltages for operation of the memory sub-system 104 based on a PMIC supply voltage. The voltages to be output can, in a number of embodiments, be determined based on conversion of the PMIC supply voltage to one or more reduced voltages corresponding to voltages compatible with operation of one or more components of memory sub-system 104, which can include controller 105, memory components 107-1, . . . , 107-N, and/or circuitry associated therewith, such as control circuitry, input/output (I/O) circuitry, address circuitry, etc.

As used herein, stating that a voltage is “compatible with” operation of a particular component is intended to mean that supplying a higher voltage can inactivate (e.g., rupture, burn out, etc.) a fuse, a transistor, a capacitor, etc., of a component configured to operate in a lower voltage range or that supplying a lower voltage can be below a voltage threshold for operation of the component. For example, the primary supply voltage 102 can be 12V or higher and a voltage compatible with operation of the PMIC 116 and/or the components thereof can be around 4V. If a primary supply voltage of 12V or higher, for example, were input to a component compatible with operation at an uppermost voltage of 5V, such a component may be inactivated. Reduction of such a high primary supply voltage to 4V, for example, can contribute to reducing a probability of such inactivation.

The PM component 110 can include a CVD 114 coupled to the PMIC 116. The CVD 114 can be utilized for reducing the primary supply voltage 102, as described herein. The CVD 114 can be coupled to connector/interface 103. The connector/interface 103 can be utilized for input of the primary supply voltage 102 (V_(in)) from the PPS 101 and/or for output of signals to control output of the primary supply voltage 102 from the PPS 101.

The CVD 114 can be configured to receive the primary supply voltage 102 as V_(in) and provide a modified primary supply voltage (MPSV) 115 to the PMIC 116 as the PMIC supply voltage. The primary supply voltage 102 can, in a number of embodiments, be received via the connector/interface 103 from the PPS 101 of the memory sub-system 104. The MPSV 115 can be a voltage that has been converted by the CVD 114 from the primary supply voltage 102 to a voltage that is not higher than the uppermost PMIC supply voltage at which the PMIC 116 is configured to operate (e.g., a voltage within a range of 3-5V).

The CVD 114 can be configured to receive, as input, multiple different primary supply voltages that are higher than the uppermost PMIC supply voltage. For example, the primary supply voltages can range from being greater than the uppermost PMIC supply voltage (e.g., 5V) to being 240V or more at various times during operation of the memory sub-system 104. Such fluctuations in the primary supply voltage can result from various causes, such as, intended inputs of increased electrical power to the PPS 101 for performance of particular operations, unintended input and/or unregulated input of electrical power to the PPS 101, and/or inappropriate operation of the PPS 101 (e.g., contributed to by damaged and/or inoperable components thereof), among other causes.

The CVD 114 can be configured to reduce each of the different primary supply voltages when they are provided by the PPS 101 through the connector/interface 103 to provide the MPSV 115 to the PMIC 116 as the PMIC supply voltage compatible with operation of the PMIC 116. The CVD 114 can be configured to divide the different primary supply voltages to produce the MPSV 115 such that the MPSV 115 can be selectably determined to provide the PMIC supply voltage compatible with operation of the PMIC 116. For example, at the different times when each of the different primary supply voltages they are provided by the PPS 101 to the CVD 114, the CVD 114 can be configured to appropriately reduce the different primary supply voltages so as to be compatible with operation of the PMIC 116, and other memory components, by adjusting the connections of multiple capacitors included on the CVD 114, as described herein.

The multiple capacitors of the CVD 114 can be adjustably (e.g., selectably) configured into multiple configurations. Producing the MPSV 115 can be performed by selectably connecting multiple capacitors of the CVD 114 in the multiple configurations. For example, the CVD 114 can be configured to selectably adjust (e.g., reduce) the primary supply voltage 102 to the MPSV 115 via multiple series-coupled capacitors being selectably connected. The configuration of the connections and/or how many of the multiple capacitors are selectably connected can depend on how high the primary supply voltage 102 is and/or an amount that the primary supply voltage 102 is to be reduced to be compatible with operation of the PMIC 116. For example, capacitors connected (coupled) in series can be utilized for reduction of the primary supply voltage 102 to the MPSV 115 compatible with operation of the PMIC 116 in order to be output to the PMIC 116. The CVD 114 can, for example, include a PMIC power control component shown at 220 in FIG. 2 that is configured to determine the appropriate connections of the multiple capacitors to enable the appropriate output of the MPSV 115 to the PMIC 116.

The PMIC 116 can include multiple regulators operable as a voltage converter component, as described in greater detail in connection with FIG. 2. The PMIC 116 can be configured to convert the MPSV 115 received from the CVD 114 to multiple voltages, for operation of various components of the memory sub-system 104, to be output from the PMIC 116. The multiple regulators of the PMIC 116 can, in a number of embodiments, include a first regulator configured to reduce the MPSV 115 received from the CVD 114 to one or more voltages compatible with operation of memory components 107. For example, the PMIC 116 can be configured to reduce the MPSV 115 to a reduced voltage compatible with operation of an array of memory cells of the memory sub-system 104 and the reduced voltage can be selectably output from the PMIC 116 for operation of the array. The PMIC 116 can, in a number of embodiments, include a second regulator configured to increase the first MPSV 115 received from the CVD 114 for operation of one or more components of the memory sub-system 104.

The PMIC 116 of the present disclosure can include a voltage converter component. The voltage converter component can include, for example, a buck regulator, among other types of regulators, configured to operate on a first reduced voltage (e.g., the MPSV 115) and to provide a second reduced voltage compatible with operation of the memory components. The second reduced voltage can be the further reduced voltage shown at 230 and described in connection with FIG. 2. For example, the primary supply voltage 102 can be 12V and the MPSV 115 output from the CVD 114 for operation of the PMIC 116 can be 4V, and the voltage output from the PMIC 116 as the further reduced voltage 130 for operation of an array of memory cells can be around 1V. The CVD 114 can perform the first reduction in order to achieve the MPSV 115 for output to the PMIC 116 by using the CVD's 114 multiple (e.g., two or more) capacitors configured to, in a number of embodiments, be connected in a configuration to produce the MPSV 115.

For example, the MPSV 115 can be produced by selectably connecting the capacitors serially to output one third (12÷3=4) of the primary supply voltage 102. The PMIC power control component 220 of the CVD 114 can be configured to determine the appropriate connections of the multiple capacitors, for a particular level of the primary supply voltage 102, to enable the appropriate output of the first MPSV 115 based on a signal (e.g., from controller 105) designating that a supply voltage is to be provided to the PMIC 116. As such, the CVD 114 can be configured to scale (e.g., divide) the primary supply voltage 102 by a selectable ratio to provide the MPSV 115.

In a number of embodiments, memory sub-system 104 can include one or more memory components 107-1, . . . , 107-N. Memory components 107-1, . . . , 107-N can, in various embodiments, include any combination of different types of non-volatile memory (NVM) components and/or volatile memory (VM) components. For example, the memory components can include at least one array of VM cells, at least one array of NVM cells, or at least one array of the VM cells in combination with at least one array of the NVM cells. In some embodiments, the memory sub-system 104 is a storage system. An example of a storage system is an SSD. The memory sub-system 104 can, in a number of embodiments, be an SSD or the memory sub-system 104 can be formed as part of an SSD. In some embodiments, the memory sub-system 104 is a hybrid memory/storage sub-system.

Each of the memory components 107-1, . . . , 107-N can include one or more arrays of memory cells such as single level cells (SLCs) or multi-level cells (MLCs). The MLCs can, in a number of embodiments, include triple level cells (TLCs) and/or quad-level cells (QLCs). In some embodiments, a particular memory component can include both an SLC portion and an MLC portion of memory cells. Each of the memory cells can store one or more bits of data (e.g., data blocks).

An example of NVM components includes a negative-and (NAND) type flash memory. Although NVM components such as NAND type flash memory are described, the memory components 107-1, . . . , 107-N can be based on various other types of memory, such as VM. In a number of embodiments, the memory components 107-1, . . . , 107-N can be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magneto random access memory (MRAM), NAND flash memory, negative-or (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of NVM cells. A cross-point array of NVM can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point NVM can perform a write in-place operation, where an NVM cell can be programmed without the NVM cell being previously erased. Furthermore, the memory cells of the memory components 107-1, . . . , 107-N can be grouped as memory pages or data blocks that can refer to a unit of the memory component used to store data.

The PPS 101 can be an electrical power source that can supply the primary supply voltage 102 for input (V_(in)) to the memory sub-system 104 for operation of the PMIC 116 and/or the memory components 107-1, . . . , 107-N, among other components of the memory sub-system 104. The PPS 101 can, for example, be an electrical outlet, a battery, and/or an AC/DC convertor, among other possible power sources. In a number of implementations, the primary supply voltage 102 can be higher than a voltage compatible with operation of the PMIC 116.

The controller 105 can communicate with the memory components 107-1, . . . , 107-N to perform operations such as reading, writing, and/or erasing data at the memory components 107-1, . . . , 107-N and other such operations. The controller 105 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller 105 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or any other suitable processor. The controller 105 can include a processing device (e.g., processor 106) configured to execute instructions stored in local memory (not shown). The local memory of the controller 105 can include an embedded memory configured to store instructions for performing various processes, operations, logic flows, and/or routines that control operation of the memory sub-system 104, including handling communications between the memory sub-system 104 and a host (not shown). In some embodiments, the local memory can include memory registers storing memory pointers, fetched data, etc. The local memory also can include read-only memory (ROM) for storing micro-code.

While the example memory sub-system 104 shown in FIG. 1 has been illustrated as including the controller 105, in other embodiments of the present disclosure a memory sub-system 104 may not include a controller 105 and may instead rely upon external control. Such external control can, in a number of embodiments, be provided by an external host and/or by a processor or controller separate from the memory sub-system 104.

In general, the controller 105 can receive commands for operations from a host system (not shown and hereinafter referred to as a “host”) and can convert the commands for operations into instructions or appropriate commands to achieve access to the memory components 107-1, . . . , 107-N for performance of such operations. The controller 105 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and/or address translations between a logical block address and a physical block address that are associated with the memory components 107-1, . . . , 107-N. The controller 105 can communicate with the host via a physical host interface (e.g., connector/interface 103).

The memory sub-system 104 also can include additional circuitry or components that are not illustrated. The memory components 107-1, . . . , 107-N can, in a number of embodiments, include control circuitry, address circuitry, sensing circuitry, and/or input/output (I/O) circuitry by which the memory components 107 can communicate with controller 105 and/or host. The control circuitry can, for example, include a PMIC power control component shown at 220 in FIG. 2, among other control circuitry. The address circuitry can, for example, include row and column decode circuitry. As an example, in some embodiments, the address circuitry can receive an address from the controller 105 and decode the address to access the memory components 107-1, . . . , 107-N. The sensing circuitry can include, for example, circuitry by which data values can be written at and/or read from a particular memory cell corresponding to an address in a row and/or column of an array. The further reduced voltage 130 output from the PMIC 116 for operation of the memory components 107-1, . . . , 107-N (e.g., a number of arrays of memory cells) can, in a number of embodiments, be provided, as directed by the controller 105, to the memory components via designated circuitry (not shown).

In general, the computing environment 100 can include a host (not shown) that can utilize the memory sub-system 104 that includes the one or more memory components 107. In a number of embodiments, the PPS 101 can be on and/or be coupled to the host and/or the primary supply voltage 102 can come from the host. The host can provide data to be stored (written) at the memory sub-system 104 and/or can request data to be retrieved (read) from the memory sub-system 104. The memory sub-system 104 can include multiple interface connections (e.g., ports) to one or more hosts. A host can send data commands (e.g., read, write, erase, program, etc.) to the memory sub-system 104 via a port.

The host can be a computing device such as a desktop computer, laptop computer, network server, mobile device, or such computing device that includes a memory and a processing device. The host can include, or be coupled to, the memory sub-system 104 so that the host can read data from or write data to the memory sub-system 104. The host can be coupled to the memory sub-system 104 via a physical host interface (e.g., connector/interface 103). The physical host interface can include control, address, data bus components, etc., to provide an interface for passing control, address, data, and other signals between the memory sub-system 104 and the host. Examples of a physical host interface can include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The host can further utilize an NVM Express (NVMe) interface to access the memory components 107-1, . . . , 107-N when the memory sub-system 104 is coupled with the host by the PCIe interface.

FIG. 2 illustrates an example of a power management (PM) component 210. PM component 210 can be PM component 110 shown in FIG. 1. In this example, the PM component 210 can include the CVD 214 and the PMIC 216 shown in FIG. 2, which can be used to manage various power requirements of the memory sub-system 104, memory components 107-1, . . . , 107-N, and/or other electronic devices coupled thereto.

For example, the PMIC 216 can be configured to operate according to one or more configuration profiles, which can control altering a voltage received from the CVD 214 to provide one or more voltages to various memory components 107 of the memory sub-system 104. Such configuration profiles can include (e.g., store) instructions, parameters, etc., to be implemented using one or more of the regulators of the voltage convertor 225 described in further detail herein for conversion of a voltage received from the CVD 214 to a voltage compatible with operation of memory components 107 (e.g., reduced from 4V to 1V).

In a number of embodiments, a particular configuration profile of the PMIC 216 can be selected based on information about system power requirements. Such information can be received, for example, from a host (not shown) coupled to the memory sub-system 104 and/or the controller 105 of the memory sub-system 104. Non-limiting examples of system power requirements can include operating voltages for the controller 105/processor 106, functionalities of the PM component 210, and/or the memory components 107, including arrays of memory cells, sensing circuitry, ASICs, state machines, etc., control signals such as voltage signals, control logic, timing signals, and/or other control signals that correspond to particular configuration profiles, power mode (e.g., sleep mode) sequencing, master/slave configurations, serial ATA (SATA) input voltages, peripheral component interconnect express (PCIe) input voltages, power backup operations, timing characteristics, operational characteristics, etc. Some system power requirements can be controlled by the controller 105, the processing device 106 thereof, the CVD 214, and/or the PMIC 216 of the PM component 210 based on configuration profiles that are provided by (e.g., stored on) the CVD 214 and/or the PMIC 216.

The CVD 214 of the PM component 210 can store multiple configuration profiles that can be dynamically selected based on various requirements resulting from changes to a magnitude of the primary supply voltage 202 input from the PPS 201 to the memory sub-system 104 via the CVD 214. As used herein, a “configuration profile” generally refers to a protocol, a set of operating voltages, master/salve configuration, power backup state, specification, or other information corresponding to operation of a host or another component, such as a memory sub-system 104 (e.g., an SSD), a video card, an audio card, or other computer component 107, such as one or more arrays of memory cells, sensing circuitry for the arrays, etc. For example, aspects of the present disclosure include the PM component 210 (e.g., the CVD 214 and/or the PMIC 216 of the PM component 210) having memory, such as NVM, disposed thereon. Such memory for the CVD 214 is shown in FIG. 2, for example, at 220 as a PMIC power control component (PPCC).

For example, the memory of the CVD 214 can be configured to store multiple selectable configuration profiles that can correspond to multiple different profiles for connection of the multiple capacitors 222 of the CVD 214. A particular profile of the multiple different profiles to implement for connection of the multiple capacitors 222 can be selected dependent upon the magnitude of the primary supply voltage 202 input (e.g., via the connector/interface 103) from the PPS 201 to the CVD 214. For example, input of a primary supply voltage 202 above a range of voltages compatible with operation of the PMIC 216 can result in selection of a particular profile stored on the PPCC 220 of the CVD 214 that includes instructions to enable connection of a certain number of the multiple capacitors 222 so as to provide a reduced output voltage 215 (e.g., the MPSV) compatible with operation of the PMIC 216. Any number of the multiple capacitors 222 can have the same capacitance and/or different capacitances.

Implementation of the CVD 214 described herein can enable use of components of the PMIC 216 (e.g., components of the voltage converter 225) designed for and/or compatible with operation within a limited range of PMIC supply voltages, where the range of voltages of the primary supply voltage 202 input to the CVD 214 can be broader and/or higher than the range of the PMIC supply voltages. For example, the range of PMIC supply voltages can be 3-5V, whereas the range of voltages input to the CVD 214 can be 12V to 240V or more. Accordingly, PMIC components designed to operate within a limited range of PMIC supply voltages can be utilized for PM components 210 without being reprogrammed and/or reconfigured based upon a particular input primary supply voltage 202 of a particular memory sub-system 104 that is above the range with which the PMIC component is compatible. Hence, utilizing the PMIC components designed as such for PM component 210 can reduce a number of the PMIC components designed as such from being wasted in stockpiles. Implementation of the CVD 214 described herein also can reduce use of PMIC components designed for a broader range of PMIC supply voltages and/or designed to perform a larger voltage reduction (e.g., from 12V to 1V rather than from 4V to 1V). Such one-stage voltage reductions using a single voltage converter of a PMIC component can be less energy efficient than the two-stage reduction using the CVD 214 described herein in combination with a voltage converter component 225 of the PMIC 216 configured to perform a smaller voltage reduction (e.g., from 5-3V to 1V).

Embodiments of a PMIC 216 consistent with this disclosure can include one or more components configured to provide multiple levels of electrical power (e.g., voltages) that are compatible with operation of memory components 107, among others, of the memory sub-system 104. The PMIC 216 can, in a number of embodiments, include a voltage detector 233 and a voltage converter component 225. The embodiment of the PMIC 216 illustrated in FIG. 2 is shown by way of example and embodiments are not limited as such. Hence, a PMIC consistent with this disclosure can include more or less components than are shown in FIG. 2.

The voltage detector 233 can detect whether the MPSV 215 exceeds a range of voltages compatible with operation of the PMIC 216. The voltage detector 233 can generate a power-off signal 224 based on a result of detection of such a MPSV 215. The power-off signal 224 can, in a number of embodiments, be sent to enable a disconnect of the PPS 201, the connector/interface 103, and/or the CVD 214 from supplying such a MPSV 215. The voltage detector 233 can include a comparator that compares the MPSV 215 to a reference voltage and outputs the power-off signal 224 as a result of the comparison. For example, when an uppermost voltage (e.g., MPSV 215) compatible with operation of the PMIC 216 is 5V, the reference voltage can be set to 5V. A range of MPSVs 215 and a corresponding reference voltage can, in a number of embodiments, be set to various voltage magnitudes. The comparator can, in some embodiments, generate the power-off signal 224 at a logic high level when the MPSV 215 is higher than a first reference voltage and can generate the power-off signal 224 at a logic low level when the MPSV 215 is lower than a second reference voltage. The first reference voltage can, for example, be higher than the second reference voltage.

The voltage converter component 225 can convert the MPSV 215 into a further reduced voltage 230 compatible with operation of the memory components 107 described herein. The MPSV 215 can be a reduced voltage relative to a voltage that was originally provided to the CVD 214 from the PPS 201. The voltage converter component 225 can include a low-dropout (LDO) regulator 226, a buck-boost converter 227, a buck regulator 228, and/or a boost regulator 229.

The LDO regulator 226 can be a linear voltage regulator that operates with a very small input-output differential voltage that can regulate an output voltage of the buck-boost converter 227 to output the further reduced voltage 230. Multiple LDO regulators 226 can be provided based on the number of further reduced voltages 230 that are used in the memory sub-system 104 of FIG. 1.

The buck-boost converter 227 can detect the MPSV 215 and can operate in a buck-mode when the MPSV 215 is higher than an intended further reduced voltage 230 to be output from the buck-boost converter 227. The buck-boost converter 227 can operate in a boost-mode when the detected MPSV 215 is lower than an intended voltage to be output from the buck-boost converter 227. The buck-boost converter 227 can contribute to output of a constant voltage in a number of embodiments.

The buck regulator 228 can be a voltage reduction-type direct current (DC)/DC converter that can generate a predetermined output voltage by reducing an input voltage (e.g., reducing the MPSV 215 to the further reduced voltage 230). The buck regulator 228 can use a switching device that is turned on/off in a certain period and can have a structure in which an input power supply (e.g., the MPSV 215) is connected to a circuit while the switch is turned on and is not connected to the circuit while the switch is turned off. The buck regulator 228 can output a DC voltage by averaging, through an inductor-capacitor (LC) filter, a voltage having a pulse shape that is periodically connected to or disconnected from a circuit in this manner. The buck regulator 228 can use a principle of generating an output voltage by averaging a pulse voltage by periodically chopping a DC voltage such that the output voltage of the buck regulator 228 (e.g., the further reduced voltage 230) can have a voltage that is less than an input voltage (e.g., the first MPSV 215) of the buck regulator 228.

The boost regulator 229 can be a voltage boost-type DC/DC converter. In the boost regulator 229, when a switch is turned on, the MPSV 215 can be connected to two terminals of an inductor to form a charge current. When the switch is turned off, the charge current can be transferred to a load. Accordingly, the amount of current of an output terminal of the boost regulator 229 can be less than that of an input terminal of the boost regulator 229. Since there is no loss due to an operation principle of the boost regulator 229, an output voltage of the boost regulator 229 can be higher than an input voltage (e.g., the MPSV 215) of the boost regulator 229, based on an “input current*input voltage=output current*output voltage” relationship.

The CVD 214 can be coupled to the PMIC 216 and can be configured to decrease a primary supply voltage 202, received from the PPS 201, to the MPSV 215. The decrease can be selectably determined to provide the PMIC 216 with a supply voltage that is lower than the primary supply voltage 202 and that is compatible with operation of the PMIC 216.

The CVD 214 can be configured to, based on a status of the primary supply voltage 202 being monitored by a monitoring unit 219 that is part of the CVD 214, provide signals to select between multiple different connections of the multiple capacitors 222 of the CVD 214. Responsive to a determination by the monitoring unit 219 that the primary supply voltage 202 is above a range of voltages compatible with operation of the PMIC 216, the monitoring unit 219 can send a signal to the PPCC 220 that is part of the CVD 214. The PPCC 220 can, in a number of embodiments, be configured to determine a particular number of (e.g., which of) the multiple capacitors 222 of the CVD 214 to connect to reduce a particular voltage magnitude of the primary supply voltage 202 to the MPSV 215 compatible with operation of the PMIC 216, direct the CVD 214 to connect the particular number of the multiple capacitors 222, and direct the CVD 214 to output the MPSV 215 to the PMIC 216.

Responsive to a determination by the monitoring unit 219 that the primary supply voltage 202 is above a voltage magnitude and/or voltage range in which the CVD 214 is configured to modify the primary supply voltage 202 to a voltage less than or equal to the uppermost PMIC 216 supply voltage, the monitoring unit 219 can, in a number of embodiments, be configured to send a signal (e.g., to the connector/interface 103) to interrupt and/or block input of the primary supply voltage 202. For example, the primary supply voltage 202 can be interrupted and/or blocked when a particular number of the multiple capacitors 222 of the CVD 214 is not enough to divide a particular voltage magnitude of the primary supply voltage 202 (e.g., because the primary supply voltage 202 is too high for the particular number of capacitors), and/or when none of the multiple different connections of the multiple capacitors 222 are configurable to divide the particular voltage magnitude of the primary supply voltage 202, to provide a particular MPSV 215 in a range of voltages compatible with operation of the PMIC 216. The monitoring unit 219 can, in a number of embodiments, be configured to send a signal to the PPCC 220 to alternatively modify the primary supply voltage 202 to produce the MPSV 215 and/or to reduce (e.g., prevent) output of a MPSV 215 from the CVD 214 to the PMIC 216. Alternatively modifying the primary supply voltage 202 can, for example, be performed using a differently configured CVD, among other possible alternatives. Interrupting and/or blocking input of the primary supply voltage 202, alternatively modifying the primary supply voltage 202, and/or preventing output of the MPSV 215 can reduce potential damage to the PMIC 216 (e.g., components of the voltage converter 225).

FIG. 3 is a flow diagram of an example method 335 to operate a CVD, as shown at 114 in FIG. 1 and at 214 in FIG. 2, in accordance with some embodiments of the present disclosure. The method 335 can be performed by processing logic that can include hardware, software (e.g., instructions run or executed on a processing device), or a combination thereof. Such hardware can, in a number of embodiments, include one or more of a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.

In a number of embodiments, the method 335 can be performed by one or more components of the controller 105, the processor 106, and/or the PM component shown at 110 and described in connection with FIG. 1 and/or shown at 210 and described in connection with FIG. 2. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes in the method 335 can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At block 336, the processing device receives a determination of a magnitude of the primary supply voltage 202. The primary supply voltage 202 can be higher than an uppermost supply voltage at which the PMIC 216 is configured to operate. The primary supply voltage 202 can, in a number of embodiments, be input to the CVD 214 on the memory sub-system 104 (e.g., SSD). The magnitude of the primary supply voltage 202 can, in a number of embodiments, be determined by a voltage detector (not shown) formed as part of the monitoring unit 219 that is part of the CVD 214, as part of the connector/interface 103, the controller 105, and/or the processor 106, or elsewhere on the memory sub-system 104. The CVD 214 can be coupled to a PMIC 216 of the memory sub-system 104.

At block 337, the processing device selectably provides, by the CVD 214, a MPSV 215 to the PMIC 216 as a PMIC supply voltage. In a number of embodiments, the MPSV 215 is not higher than the uppermost supply voltage at which the PMIC 216 is configured to operate.

In a number of embodiments, the processing device directs selectably reducing the MPSV 215, using a voltage converter component 225 of the PMIC 216, to a further reduced voltage compatible with operation of a selected memory component 107 of the memory sub-system 104.

In a number of embodiments, the processing device of the memory sub-system 104 can be configured to receive instructions, from a host separate from the memory sub-system 104, for performance of an operation on the selected memory component 107 of the memory sub-system. The processing device of the memory sub-system 104 can be further configured to direct performance of the operation. The operation can be selectably performed by a PPCC 220 of the CVD 214 directing the CVD 214 to perform an adjustment on the primary supply voltage 202 to cause the MPSV 215 to be within a predetermined range of voltages compatible with operation of the PMIC 216.

FIG. 4 is an additional flow diagram 440 of the example method 350 illustrated in FIG. 3 in accordance with some embodiments of the present disclosure. At block 442, the processing device directs performance, by the CVD 214, of a coarse adjustment on the primary supply voltage 302 received from the PPS 201 to cause a reduced voltage to be within a predetermined range of voltages compatible with operation of the PMIC 216. At block 443, the processing device directs performance, by the PMIC 216, of a fine adjustment on the reduced voltage received from the CVD 214 to cause a further reduced voltage to be within a predetermined range of voltages compatible with performance of an operation on a selected memory component 107 (e.g., an array of memory cells) on the memory sub-system 104.

At block 444, the performance of the coarse adjustment can include the predetermined range of voltages compatible with operation of the PMIC 216 being wider than the predetermined range of voltages compatible with operation of the selected array that is caused by the fine adjustment. For example, the coarse adjustment can cause a voltage of 12V to be reduced by the CVD 214 to the reduced voltage (e.g., the MPSV 215) having a 3-5V range compatible with operation of the PMIC 216, whereas the fine adjustment performed by the PMIC 216 can cause the further reduced voltage to be within a 0.5-1.5V range compatible with operation of the selected array. The coarse adjustment just described can, in a number of embodiments, be performed on a primary supply voltage 202 that is not reduced below a threshold voltage to provide the MPSV 215 having the 3-5V range. For example, the coarse adjustment can be performed on a primary supply voltage 202 with a magnitude of 12V that is within a normal operating range of input voltages.

At block 445, the performance of the fine adjustment can include the values of the further reduced voltages that are compatible with performance of the number of operations on the selected array being less than the values of the reduced voltages (or the MPSV 215) that are compatible with operation of the PMIC 216. For example, the magnitude of the voltages in the 0.5-1.5V range compatible with operation of the selected array is less than the magnitude of the voltages in the 3-5V range compatible with operation of the PMIC 216.

FIG. 5 illustrates an example machine of a computer system 550 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system 550 can correspond to a host system (e.g., the host system described in connection with FIG. 1) that includes, is coupled to, and/or utilizes a memory sub-system such as the memory device/SSD 104 of FIG. 1. The computer system 550 can be used to execute operations of a controller 105 and/or processor 106 on an operating system to perform operations, including the operations performed by the PM component 110 of FIG. 1 and/or the PM component 210 of FIG. 2). In a number of embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 550 includes a processing device 552, a main memory 554, a static memory 558, and a data storage system 502, which communicate with each other via a bus 557. The main memory 554 can, in a number of embodiments, be read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), among other possibilities. The static memory 558 can, in a number of embodiments, be flash memory, static random access memory (SRAM), among other possibilities. The data storage system 502 can correspond to the memory sub-system 104, the memory device, and/or the SSD described in connection with FIG. 1.

Processing device 552 can represent one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 552 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 552 is configured to execute instructions 553 for performing the operations and steps discussed herein. The computer system 550 can further include a network interface device 555 to communicate over a network 556.

The data storage system 502 can include a machine-readable storage medium 559 (also known as a computer-readable medium) on which is stored one or more sets of instructions 553 or software embodying any one or more of the methodologies or functions described herein. The instructions 553 also can reside, completely or at least partially, within the main memory 554 and/or within the processing device 552 during execution thereof by the computer system 550. The main memory 554 and the processing device 552 also contribute to the machine-readable storage media. The machine-readable storage medium 559, data storage system 502, and/or main memory 554 can correspond to the memory sub-system 104 of FIG. 1.

In a number of embodiments, the instructions 553 can include instructions to implement functionalities corresponding to a power management component. The functionalities can, for example, correspond to the functionalities of the PM component 210 of FIG. 2, including the CVD 214 and the PMIC 216, among others. While the machine-readable storage medium 559 is shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that can cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data values (bits) within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description herein. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable storage medium, such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. 

What is claimed is:
 1. A memory sub-system, comprising: a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system, the PMIC configured to output a plurality of voltages for operation of the memory sub-system based on a PMIC supply voltage; and a capacitive voltage divider (CVD) coupled to the PMIC, the CVD configured to: receive the primary supply voltage of the memory sub-system as an input; and provide a modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, wherein the MPSV is not higher than the uppermost PMIC supply voltage.
 2. The memory sub-system of claim 1, wherein the memory sub-system is a solid-state drive (SSD).
 3. The memory sub-system of claim 1, wherein the CVD is further configured to receive, as the input, a plurality of different primary supply voltages that are higher than the uppermost PMIC supply voltage.
 4. The memory sub-system of claim 3, wherein the CVD is further configured to reduce each of the plurality of different primary supply voltages to provide the MPSV to the PMIC as the PMIC supply voltage compatible with operation of the PMIC.
 5. The memory sub-system of claim 1, wherein the CVD is further configured to scale the primary supply voltage, received via a connector from a primary power supply, by a selectable ratio to provide the MPSV.
 6. The memory sub-system of claim 1, wherein the MPSV is selectably determined to provide the PMIC supply voltage as compatible with the operation of the PMIC.
 7. The memory sub-system of claim 1, wherein the PMIC comprises: a first regulator configured to reduce the MPSV received from the CVD; and a second regulator configured to increase the MPSV received from the CVD.
 8. The memory sub-system of claim 1, wherein the PMIC is further configured to reduce the MPSV received from the CVD to a reduced voltage compatible with operation of the memory sub-system.
 9. The memory sub-system of claim 8, wherein the reduced voltage is selectably output from the PMIC for operation of the memory sub-system.
 10. The memory sub-system of claim 1, wherein the CVD is further configured to selectably adjust the primary supply voltage to the MPSV via a plurality of series-coupled capacitors.
 11. The memory sub-system of claim 1, wherein the PMIC is further configured to convert the MPSV, received from the CVD, to the plurality of voltages to be output from the PMIC for operation of the memory sub-system.
 12. A memory sub-system, comprising: a capacitive voltage divider (CVD) configured to decrease a primary supply voltage received from a primary power supply (PPS) of the memory sub-system; wherein the decrease is selectably determined to provide a power-management integrated circuit (PMIC) supply voltage that is lower than the primary supply voltage and that is compatible with the operation of the PMIC.
 13. The memory sub-system of claim 12, wherein the memory sub-system is a solid-state drive (SSD).
 14. The memory sub-system of claim 12, wherein the CVD is further configured to convert the primary supply voltage to a modified primary supply voltage (MPSV) by reduction of the primary supply voltage.
 15. The memory sub-system of claim 14, wherein the PMIC is configured to convert the MPSV to a further reduced voltage by further reduction of the MPSV.
 16. The memory sub-system of claim 15, further comprising: a plurality of memory components operably coupled to the CVD; wherein the PMIC is further configured to output the further reduced voltage to power the plurality of memory components.
 17. The memory sub-system of claim 12, wherein: the CVD comprises a plurality of capacitors; and the CVD is further configured to, based on a status of the primary supply voltage being monitored, provide signals to select between the plurality of capacitors to enable output of a modified primary supply voltage (MPSV) to the PMIC.
 18. A method, comprising: receiving a primary supply voltage that is higher than an uppermost supply voltage at which a power management integrated circuit (PMIC) is configured to operate; and selectably providing, by a capacitive voltage divider (CVD), a modified primary supply voltage (MPSV) to the PMIC as a PMIC supply voltage, wherein the MPSV is not higher than the uppermost supply voltage at which the PMIC is configured to operate.
 19. The method of claim 18, further comprising selectably reducing the MPSV, using a voltage converter of the PMIC, to a further reduced voltage compatible with operation of a selected memory component of the SSD.
 20. The method of claim 18, further comprising: performing, by the CVD, a coarse adjustment on the primary supply voltage received from a primary power supply to cause a reduced voltage to be within a predetermined range of voltages compatible with operation of a PMIC; and performing, by the PMIC, a fine adjustment on the reduced voltage received from the CVD to cause a further reduced voltage to be within a predetermined range of voltages compatible with performance of an operation on a selected array of memory cells on the SSD; and wherein: performing the coarse adjustment includes the predetermined range of voltages compatible with operation of the PMIC being wider than the predetermined range of voltages compatible with operation of the selected array that is caused by the fine adjustment; and performing the fine adjustment includes the values of the further reduced voltages that are compatible with performance of the number of operations on the selected array being less than the values of the reduced voltages that are compatible with operation of the PMIC.
 21. The method of claim 18, further comprising: configuring a processing device of the SSD to receive instructions, from a host separate from the SSD, for performance of an operation on a selected memory component of the SSD and to direct performance of the operation by: a PMIC power control component of the CVD selectably directing the CVD to perform an adjustment on the primary supply voltage to cause the MPSV to be within a predetermined range of voltages compatible with operation of the PMIC. 